StrichLux/IO-ETH

The StrichLux IO-ETH module will provide 1-4 universes of input or output via Art-Net initially, but may support other protocols later. This module can "take over" adjacent channels if configured to, so that only one module is needed for a complete StrichLux system.

Project Status

• 2013-09: Used for the LED wall display at Maker Faire Toronto 2013. One box failed in use, seems to be soldering on the PHY. Need to redesign this a bit to get rid of the QFN'ed PHY.
• 2013-05: On hold for how due to too many other paying/deadlined projects. Will resume when working on invisibleMaze.
• 2012-08: Used at BRC2012 in Beacon4, worked as-expected except that all boards were programmed with the same MAC address! Need to get dynamic configuration via CORE, as well as get the status display code written and working.
• 2012-07-21: Built a bunch more for the Beacon4 project.
• 2012-07-08: All working! :)
• 2012-07-01: Status LED driving code written, as well as code to do the initialization handshake/negotiation with the CORE. Will test it all tomorrow at the lab.
• 2012-06-29: After numerous software fixes, the board works! Now receiving ArtDmx packets and sending SPI. A few more tweaks required, then integration testing with the StrichLux/CORE.
• 2012-06-27: Borrowed a dev board from Andrew to confirm whether hardware or software was the culprit. Now have node discovery (ArtPoll/ArtPollReply) functionality working on the dev board, Lightjams successfully discovers the node. Hardware investigation will have to be done next time I'm at the lab.
• 2012-06-23: Link obtained after many code fixes. Still no data transfer working.
• 2012-06-22: Another evening of testing, found issue (worked around) with the display, fixed many software issues, but still no Ethernet link yet. Suspect (after I left the lab) that a missing SYSTEMConfigPerformance() call may be the culprit.
• 2012-06-21: PCBs and parts are here, assembled the first board. No time to test, will have to do that tomorrow. Firmware is ~10% complete.
• 2012-05-27: Routing done, checklist run, CAM processing done, sent off to MyRO for PCB manufacturing. Still need to order parts.
• 2012-05-26: Schematic/BOM complete, routing starting.
• 2012-05-25: Started schematic.
• 2012-05-01: Renamed from IO-ArtNet to IO-ETH, as I may support ACN or other protocols later.
• 2012-04-24: Started initial planning.

Specs

• Based around the PIC32MX664F128H microcontroller as there is no economical way to do Ethernet on FPGAs for low-cost designs
• This micro has no EEPROM (?!) so will need external I2C EEPROM for storing config data
  • Using one with a MAC address burns in solves the problem of needing an IAB too
• Also needs external PHY
  • LAN8720C is supported, small, and inexpensive, so it seems a good choice

Rev. 1 Issues

• Ethernet termination resistors are shown as 75 on the schematic, but (correctly) 49.9 on BOM
• C5 is under the crystal!
• LED display common wired to GND, but it's a common anode unit (can switch from ACSA to ACSC model until the board gets redone)
• Main status LED is backwards (anodes to GND, cathodes to PIC pins)
• Ethernet jack LEDs are backwards
• Hugely labour intensive to assemble, need to switch to using resistor packs wherever possible