Difference between revisions of "StrichLux/IO-SPI"
From Hackstrich
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(Ordered boards.) |
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== Project Status == | == Project Status == | ||
| + | * 2012-07-19: Greenwired a revision 1 board into a partly-revision-2 board and it works (only on SCLK channel, but that's enough of a test). Reviewed gerbers and submitted to MyRO. Expected date is next Friday (July 27th). | ||
* 2012-07-10: Finished revision 2 of the board, waiting until tomorrow to review and submit it. | * 2012-07-10: Finished revision 2 of the board, waiting until tomorrow to review and submit it. | ||
* 2012-07-05: Rewrote all SPI logic to use a custom Verilog SPI core rather than the EFB. Now fully working! | * 2012-07-05: Rewrote all SPI logic to use a custom Verilog SPI core rather than the EFB. Now fully working! | ||
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[[Category:Current Projects]] | [[Category:Current Projects]] | ||
| − | [[Category:Status/Waiting for | + | [[Category:Status/Waiting for Boards]] |
Revision as of 12:00, 19 July 2012
The StrichLux IO-SPI module will provide one universe of SPI output for the StrichLux system, mainly for use driving addressable LED strips. Initially it will only support output, but the hardware supports output, so it could be implemented later.
Project Status
- 2012-07-19: Greenwired a revision 1 board into a partly-revision-2 board and it works (only on SCLK channel, but that's enough of a test). Reviewed gerbers and submitted to MyRO. Expected date is next Friday (July 27th).
- 2012-07-10: Finished revision 2 of the board, waiting until tomorrow to review and submit it.
- 2012-07-05: Rewrote all SPI logic to use a custom Verilog SPI core rather than the EFB. Now fully working!
- 2012-07-04: CORE interface code written, but not working yet. Clock seems to glitch when frequency is adjusted, and the logic analyzer is showing 0x0E being transmitted for some reason. More work to continue tomorrow.
- 2012-06-06: Modularized the SPI transceiver code and got it all working this way. Should be relatively simple to add the interface code to get data from the framebuffer now.
- 2012-06-03: More troubleshooting, got the code working and it controls the LEDs! Flaky hardware-wise though because the level shifter can only sink 10uA, and the strips want 50uA to reliably drive. Need to order another level shifter without the automatic direction feature and test it.
- 2012-06-02: Lots of troubleshooting, not quite there yet. Was hanging after one cycle, which is now fixed/working in the simulator. Need to re-test against real hardware next time I'm at the lab.
- 2012-06-01: Assembled and started testing.
- 2012-05-31: Boards are here!
- 2012-05-24: Parts ordered and received. Still waiting for boards.
- 2012-04-29: Finished schematic, done board layout, checklists run, sent to Laen for manufacturing. Parts still need to be ordered.
- 2012-04-28: Started schematicizing and BOM selection.
- 2012-04-24: Started initial planning.
Specs
- Based around the Lattice MachXO2-256 CPLD (common to other IO modules)
- Will pass power through from one of the high power busses
- Needs to handle 50W! (4.25A @ 12V or 10A @ 5V)
- JST SM seems to be a common connector for these
- But it's wire-to-wire only, no PCB mount version available
- Using a 2x3 Mini-Fit Jr. connector instead, 6 pins so it can carry a full SPI bus (MISO/MOSI/!SS/SCLK) plus power
Rev. 1 Issues
- Fixed on revision 2 -
Missing silkscreen on U1 - Fixed on revision 2 -
TDO/TDI connect to the wrong pins - Fixed on revision 2 -
SN needs to be tied high - Fixed on revision 2 -
Auto-switching level shifter can't drive enough current to drive LED strips - Fixed on revision 2 -
Interface-side of level shifter needs to be tied to idle state through 10k - Fixed on revision 2 -
Bus A and Bus B labels are swapped
Architecture
<graph>graph {output: svg;}[ SPI Hardened Core ] <-- Wishbone --> [ Module Controller Softcore ]</graph>
