Difference between revisions of "ECLair"

Revision as of 21:31, 9 December 2012

ECLair is a long-term project to build an ECL minicomputer.

2012-12-08: Added decode support for ROM/RAM/device memory, got everything working so that now an instruction is fetched from ROM at startup and is jumped to in microcode. Started work on the X/Y registers, and started work on a microcode generator so I can stop typing in individual bits.
2012-12-05: Got the part that's been diagrammed into Verilog and working. Now fetches instructions (from a constant right now, not RAM yet) and does jumps to their location in microcode.
2012-12-04: Started the logical diagram and the microcode layout.
2012-12-01/02: Spent the weekend reading Bit-Slice Microprocessor Design.
2012-11-24: Basic ideas/architecture starting to get put together.

MECL-based (tentatively 10KH levels/speeds)
25MHz main clock
8-bit data width
24-bit physical address, 16-bit virtual address
DMA support (at least for front panel, maybe one other DMA channel?)
Microcoded, running control store in SRAM for speed
- Unless I can find equally-fast EPROMs
- Copied to SRAM from EPROM before the system releases reset on powerup

Bit #	Width	Function	Details
0	1	MC Addr Source	low = microcode bits, high = IR
1	1	Jump MC Addr	Microcode sequencer load
2-9	8	MC Jump Address	Used if bit 0 = low
10	1	MAR Source	low = PC, high = Z
11	1	MDR Source	low = data bus, high = Z
12	1	MDR Load	MDR latch load
13	1	MAR Load	MAR latch load (source specified by bit 10)
14	1	IR Load	IR latch load from data bus
15	1	PC Increment	Increment PC by 1
16	1	PC Load	PC counter load from Z
17-19	3	Register Load from Z	000 - None 001 - A 010 - B 011 - C 100 - D 101 - SP 110 - MAR
20-23	4	ALU Operation	1111 - Z=X
24	1	RAM Read
25	1	RAM Write
26-28	3	X/Y Register Source	000 - Immediate Zero 001 - A 010 - B 011 - C 100 - D 101 - SP 110 - MAR
29-30	2	AVAILABLE
31	1	X Load
32	1	Y Load
33	1	Z Load

@@ Line 134: / Line 134: @@
 | Y Load
 |
+|-
+| 33
+| 1
+| Z Load
+|
 |}
 [[Category:Current Projects]]