Difference between revisions of "ECLair"
From Hackstrich
(25 is now high byte MDR load, 12 is now load byte MDR load) |
(MAR and MDR don't need to be in the reg load bits, they have their own bits) |
||
| Line 101: | Line 101: | ||
| 3 | | 3 | ||
| Register Load from Z | | Register Load from Z | ||
| − | | 000 - None<br>001 - A<br>010 - B<br>011 - C<br>100 - D<br>101 - SP | + | | 000 - None<br>001 - A<br>010 - B<br>011 - C<br>100 - D<br>101 - SP |
|- | |- | ||
| 20 | | 20 | ||
Revision as of 17:40, 16 December 2012
ECLair is a long-term project to build an ECL minicomputer.
Project Status
- 2012-12-15: Found bug in the datasheet of the MC10H181, fixed it and now the ALU checks out completely. Started integrating it into the CPU. Next step is to finish the MDR-XY data path so that Load Immediate instruction can be implemented, then Add can be implemented/tested.
- 2012-12-14: Verilog transcription of ALU almost complete, but malfunctioning in the carry logic of the second bit. Will be using MC10H181 w/ MC10H179 CLA generator.
- 2012-12-09: Started working on ALU design/verilog transcription.
- 2012-12-08: Added decode support for ROM/RAM/device memory, got everything working so that now an instruction is fetched from ROM at startup and is jumped to in microcode. Started work on the X/Y registers, and started work on a microcode generator so I can stop typing in individual bits.
- 2012-12-05: Got the part that's been diagrammed into Verilog and working. Now fetches instructions (from a constant right now, not RAM yet) and does jumps to their location in microcode.
- 2012-12-04: Started the logical diagram and the microcode layout.
- 2012-12-01/02: Spent the weekend reading Bit-Slice Microprocessor Design.
- 2012-11-24: Basic ideas/architecture starting to get put together.
Architecture Overview
- MECL-based (tentatively 10KH levels/speeds)
- 25MHz main clock
- 8-bit data width
- 24-bit physical address, 16-bit virtual address
- DMA support (at least for front panel, maybe one other DMA channel?)
- Microcoded, running control store in SRAM for speed
- Unless I can find equally-fast EPROMs
- Copied to SRAM from EPROM before the system releases reset on powerup
Memory Map
- 24bit / 16MB address space
- 14MB for RAM, 1MB for ROM, 1MB for memory-mapped devices
- 0x000000 - 0xEFFFFF - ROM
- 0x100000 - 0x0FFFFF - RAM
- 0x200000 - 0x1FFFFF - RAM
- 0x300000 - 0x2FFFFF - RAM
- 0x400000 - 0x3FFFFF - RAM
- 0x500000 - 0x4FFFFF - RAM
- 0x600000 - 0x5FFFFF - RAM
- 0x700000 - 0x6FFFFF - RAM
- 0x800000 - 0x7FFFFF - RAM
- 0x900000 - 0x8FFFFF - RAM
- 0xA00000 - 0x9FFFFF - RAM
- 0xB00000 - 0xAFFFFF - RAM
- 0xC00000 - 0xBFFFFF - RAM
- 0xD00000 - 0xCFFFFF - RAM
- 0xE00000 - 0xDFFFFF - RAM
- 0xF00000 - 0xFFFFFF - Devices
Microcode Layout
| Bit # | Width | Function | Details |
|---|---|---|---|
| 0 | 1 | MC Addr Source | low = microcode bits, high = IR |
| 1 | 1 | Jump MC Addr | Microcode sequencer load |
| 2-9 | 8 | MC Jump Address | Used if bit 0 = low |
| 10 | 1 | MAR Source | low = PC, high = Z |
| 11 | 1 | MDR Source | low = data bus, high = Z |
| 12 | 1 | MDR Load Low Byte | Latches data or Z (determined by bit 11) into low byte of MDR |
| 13 | 1 | MAR Load | MAR latch load (source specified by bit 10) |
| 14 | 1 | IR Load | IR latch load from data bus |
| 15 | 1 | PC Increment | Increment PC by 1 |
| 16 | 1 | PC Load | PC counter load from Z |
| 17-19 | 3 | Register Load from Z | 000 - None 001 - A 010 - B 011 - C 100 - D 101 - SP |
| 20 | 1 | ALU Mode | 0 = Arithmetic, 1 = Logic |
| 21-24 | 4 | ALU Operation | 1111 - Z=X |
| 25 | 1 | MDR Load High Byte | Latches data or Z (determined by bit 11) into high byte of MDR |
| 26-28 | 3 | X/Y Register Source | 000 - Immediate Zero 001 - A 010 - B 011 - C 100 - D 101 - SP 110 - MAR 111 - MDR |
| 29 | 1 | RAM Read | |
| 30 | 1 | RAM Write | |
| 31 | 1 | X Load | |
| 32 | 1 | Y Load | |
| 33 | 1 | Z Load |
