Difference between revisions of "ECLair"

From Hackstrich
(Microcode bit 10 changed.)
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| Register Load from Z
 
| Register Load from Z
| 000 - None<br>001 - A<br>010 - B<br>011 - C<br>100 - D<br>101 - SP
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| 000 - None<br>001 - A<br>010 - B<br>011 - C<br>100 - D<br>101 - SP<br>110 - MAR
 
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| 20-23
 
| 20-23

Revision as of 00:18, 9 December 2012

ECLair is a long-term project to build an ECL minicomputer.

Project Status

  • 2012-12-05: Got the part that's been diagrammed into Verilog and working. Now fetches instructions (from a constant right now, not RAM yet) and does jumps to their location in microcode.
  • 2012-12-04: Started the logical diagram and the microcode layout.
  • 2012-12-01/02: Spent the weekend reading Bit-Slice Microprocessor Design.
  • 2012-11-24: Basic ideas/architecture starting to get put together.

Architecture Overview

  • MECL-based (tentatively 10KH levels/speeds)
  • 25MHz main clock
  • 8-bit data width
  • 24-bit physical address, 16-bit virtual address
  • DMA support (at least for front panel, maybe one other DMA channel?)
  • Microcoded, running control store in SRAM for speed
    • Unless I can find equally-fast EPROMs
    • Copied to SRAM from EPROM before the system releases reset on powerup

Memory Map

  • 24bit / 16MB address space
  • 14MB for RAM, 1MB for ROM, 1MB for memory-mapped devices
  • 0x000000 - 0xEFFFFF - ROM
  • 0x100000 - 0x0FFFFF - RAM
  • 0x200000 - 0x1FFFFF - RAM
  • 0x300000 - 0x2FFFFF - RAM
  • 0x400000 - 0x3FFFFF - RAM
  • 0x500000 - 0x4FFFFF - RAM
  • 0x600000 - 0x5FFFFF - RAM
  • 0x700000 - 0x6FFFFF - RAM
  • 0x800000 - 0x7FFFFF - RAM
  • 0x900000 - 0x8FFFFF - RAM
  • 0xA00000 - 0x9FFFFF - RAM
  • 0xB00000 - 0xAFFFFF - RAM
  • 0xC00000 - 0xBFFFFF - RAM
  • 0xD00000 - 0xCFFFFF - RAM
  • 0xE00000 - 0xDFFFFF - RAM
  • 0xF00000 - 0xFFFFFF - Devices

Microcode Layout

Bit # Width Function Details
0 1 MC Addr Source low = microcode bits, high = IR
1 1 Jump MC Addr Microcode sequencer load
2-9 8 MC Jump Address Used if bit 0 = low
10 1 MAR Source low = PC, high = Z
11 1 MDR Source low = data bus, high = Z
12 1 MDR Load MDR latch load
13 1 MAR Load MAR latch load from Z
14 1 IR Load IR latch load from data bus
15 1 PC Increment Increment PC by 1
16 1 PC Load PC counter load from Z
17-19 3 Register Load from Z 000 - None
001 - A
010 - B
011 - C
100 - D
101 - SP
110 - MAR
20-23 4 ALU Operation 1111 - Z=X
24 1 RAM Read
25 1 RAM Write