ECLair
From Hackstrich
ECLair is a long-term project to build an ECL minicomputer.
Project Status
- 2012-12-23: Worked out the right way to fix the sequencing issue/dependency between microcode signals, now the level-sensitive signals (bits 0-23) latch first, then the edge-sensitive signals (bits 24-63) latch, then the edge-sensitive signals are reset back to 0 so they don't mis-trigger when the level-sensitive signals change again on the next cycle. This means all edge-sensitive signals need to be active-high, but that hasn't been an issue so far.
- 2012-12-22: Hacked on the sequencing issue more, no real progress.
- 2012-12-21: Reordered microcode bits into 24 bits for edge-sensitive signals and 40 for level-sensitive signals. Redesigned the microcode sequencer to use a latch and an always-populated next_addr bit field rather than a counter, which solves many problems around jumping and runt cycles. Still don't have sequencing of the two classes of microcode bits worked out, it's proving a much harder problem than I'd expected.
- 2012-12-20: Implemented realistic propagation delays for most parts (main EPROM and ALU not done yet), and fixed a bunch of bugs related to previous lack of delays. Have a hacked-in delay for cs_jump right now, next step is to split the microcode into 24 "edge-sensitive signal bits" and 40 "level-sensitive signal bits", and clock the former slightly after the latter. This will avoid needing two separate microcode instructions to set up level-sensitive signals then trigger the edge-sensitive ones. Will mean a complete reorganization order-wise of the microcode though.
- 2012-12-19: Finished implementing 8/16-bit width selection and got the bugs worked out. Now have 8-bit and 16-bit immediate loads, and 8-bit don't trash the other 8 bits of the destination register. Still need to get 8-bit high-byte load implemented. Next step though is probably to rethink the hold_last function in the microcode assembler, should probably make it more intelligent to only hold level sensitive signals and leave the edge-sensitive ones out.
- 2012-12-18: Half-implemented 8/16-bit width selection using a microcode bit. Doesn't work yet.
- 2012-12-17: Implemented a data path from IR[7:6] to the register latch signals, so that all register-related operations can be simplified in microcode. Moved the ldi* instructions to use this new path, everything is tested and working. Next step is probably to get the 8/16-bit split working, so that 8-bit operations don't erase the other byte of the word.
- 2012-12-16: MDR-XY data path implemented, Load Immediate 8-bit values to A and B instructions written, add 16-bit A=A+B written, all working.
- 2012-12-15: Found bug in the datasheet of the MC10H181, fixed it and now the ALU checks out completely. Started integrating it into the CPU. Next step is to finish the MDR-XY data path so that Load Immediate instruction can be implemented, then Add can be implemented/tested.
- 2012-12-14: Verilog transcription of ALU almost complete, but malfunctioning in the carry logic of the second bit. Will be using MC10H181 w/ MC10H179 CLA generator.
- 2012-12-09: Started working on ALU design/verilog transcription.
- 2012-12-08: Added decode support for ROM/RAM/device memory, got everything working so that now an instruction is fetched from ROM at startup and is jumped to in microcode. Started work on the X/Y registers, and started work on a microcode generator so I can stop typing in individual bits.
- 2012-12-05: Got the part that's been diagrammed into Verilog and working. Now fetches instructions (from a constant right now, not RAM yet) and does jumps to their location in microcode.
- 2012-12-04: Started the logical diagram and the microcode layout.
- 2012-12-01/02: Spent the weekend reading Bit-Slice Microprocessor Design.
- 2012-11-24: Basic ideas/architecture starting to get put together.
Architecture Overview
- MECL-based (tentatively 10KH levels/speeds)
- 25MHz main clock
- 8-bit data width
- 24-bit physical address, 16-bit virtual address
- DMA support (at least for front panel, maybe one other DMA channel?)
- Microcoded, running control store in SRAM for speed
- Unless I can find equally-fast EPROMs
- Copied to SRAM from EPROM before the system releases reset on powerup
Memory Map
- 24bit / 16MB address space
- 14MB for RAM, 1MB for ROM, 1MB for memory-mapped devices
- 0x000000 - 0xEFFFFF - ROM
- 0x100000 - 0x0FFFFF - RAM
- 0x200000 - 0x1FFFFF - RAM
- 0x300000 - 0x2FFFFF - RAM
- 0x400000 - 0x3FFFFF - RAM
- 0x500000 - 0x4FFFFF - RAM
- 0x600000 - 0x5FFFFF - RAM
- 0x700000 - 0x6FFFFF - RAM
- 0x800000 - 0x7FFFFF - RAM
- 0x900000 - 0x8FFFFF - RAM
- 0xA00000 - 0x9FFFFF - RAM
- 0xB00000 - 0xAFFFFF - RAM
- 0xC00000 - 0xBFFFFF - RAM
- 0xD00000 - 0xCFFFFF - RAM
- 0xE00000 - 0xDFFFFF - RAM
- 0xF00000 - 0xFFFFFF - Devices
Microcode Layout
| Bit # | Width | Function | Details |
|---|---|---|---|
| Edge Sensitive Signals | |||
| 0 | 1 | AVAILABLE | |
| 1 | 1 | MDR Load Low Byte | Latches data or Z (determined by bit 11) into low byte of MDR |
| 2 | 1 | MDR Load High Byte | Latches data or Z (determined by bit 11) into high byte of MDR |
| 3 | 1 | MAR Load | MAR latch load (source specified by bit 10) |
| 4 | 1 | IR Load | IR latch load from data bus |
| 5 | 1 | PC Increment | Increment PC by 1 |
| 6 | 1 | PC Load | PC counter load from Z |
| 7-9 | 3 | Register Load from Z | 000 - None 001 - A 010 - B 011 - C 100 - D 101 - SP 111 - Value from IR[6..7] (only A-D) |
| 10 | 1 | X Load | |
| 11 | 1 | Y Load | |
| 12 | 1 | Z Load | |
| Level Sensitive Signals | |||
| 24 | 1 | AVAILABLE | |
| 25-32 | 8 | Next CS Address | 0 = Use IR |
| 33 | 1 | MAR Source | low = Z, high = PC |
| 34 | 1 | MDR Source | low = Z, high = data bus |
| 35 | 1 | ALU Mode | 0 = Arithmetic, 1 = Logic |
| 36-39 | 4 | ALU Operation | 1111 - Z=X |
| 40-42 | 3 | X/Y Register Source | 000 - Immediate Zero 001 - A 010 - B 011 - C 100 - D 101 - SP 110 - MAR 111 - MDR |
| 43 | 1 | RAM Read | |
| 44 | 1 | RAM Write | |
| 45 | 1 | Operation Width | 0 = 8-bit, 1 = 16-bit |
