Difference between revisions of "Project Checklists"

From Hackstrich
(Added more detail on what "required test points" actually means.)
(Note about making sure not to paste PTH things)
 
(8 intermediate revisions by the same user not shown)
Line 1: Line 1:
 +
== General Notes ==
 +
* If any checklist item fails and requires ''any'' change to the design, start that checklist over from the start after the change.
 +
** Really. It's important. The 2 extra minutes will save re-spinning a board.
 +
* Once checklists are all complete, wait 24 hours and take another brief look at the design before sending to manufacturing.
 +
** Don't have to re-run checklists, just look it over. It's surprising how many things jump out at you after not looking at a design for awhile.
 +
 
== Schematic Completion ==
 
== Schematic Completion ==
 
* Does the schematic pass ERC?
 
* Does the schematic pass ERC?
Line 13: Line 19:
 
** 8/16-bit test/debug bus connector for CPLD/FPGA projects that could require logic analyzer connection
 
** 8/16-bit test/debug bus connector for CPLD/FPGA projects that could require logic analyzer connection
 
* Is there a way for the user to receive status information (like LEDs)?
 
* Is there a way for the user to receive status information (like LEDs)?
* Are all nets named something useful (not N$)?  Use the SHOW @ N$* command to check.
+
* Are all nets named something useful (not N$)?  Use the SHOW @ N$* command to check, if using EAGLE.
 
* Are all nets properly classed (if required)?
 
* Are all nets properly classed (if required)?
 
* Is there a way to set the address of the board (if on a multidrop bus)?
 
* Is there a way to set the address of the board (if on a multidrop bus)?
Line 27: Line 33:
 
** Do a physical mockup if required to make sure everything fits in properly.
 
** Do a physical mockup if required to make sure everything fits in properly.
 
* Are all connectors on the correct side of the board?
 
* Are all connectors on the correct side of the board?
 +
* If the design has multiple boards with connectors between them, trace the path of a couple signals and make sure both connectors match up.
 
* Has the footprint/pinout of any new components been double checked?
 
* Has the footprint/pinout of any new components been double checked?
* Will the test points be easy to get to once the board is stuffed?
 
 
* Are all sharp bends mitered?
 
* Are all sharp bends mitered?
 
* Are all high-speed signals properly laid out?
 
* Are all high-speed signals properly laid out?
Line 41: Line 47:
 
** URL (if possible to fit)
 
** URL (if possible to fit)
 
** Revision number
 
** Revision number
 +
** ECO tracking boxes
 
** Area for serial number
 
** Area for serial number
 
** Strich
 
** Strich
* Does text on both sides of the board all face the same direction?
+
* Switch to 3D view (if using Kicad) and check the following:
 +
** Does text on both sides of the board all face the same direction?
 +
** Do labels all appropriately describe what they're next to?
 +
** Will the test points be easy to get to once the board is stuffed?
  
 
== CAM Completion ==
 
== CAM Completion ==
Line 49: Line 59:
 
* Are vias tented appropriately?
 
* Are vias tented appropriately?
 
* Does mask extend between component pins?
 
* Does mask extend between component pins?
* Are test points left exposed?
+
* Are test points left exposed on the correct side of the board?
 
* Do silkscreen layers look reasonable and non-overlapping?
 
* Do silkscreen layers look reasonable and non-overlapping?
 
* Does any silkscreen overlap drills?
 
* Does any silkscreen overlap drills?
 
* Are required ground ties in place (if required)?
 
* Are required ground ties in place (if required)?
 +
* Are break-out tabs set up correctly?
 +
* Does board outline appear correct and contiguous?
 +
* Are slots/cutouts properly set up?
 +
* Are thermal pads left exposed and not covered in solder mask?
 +
* Are PTH pads excluded from paste layers?
  
 
[[Category:Notes]]
 
[[Category:Notes]]

Latest revision as of 18:05, 30 September 2023

General Notes

  • If any checklist item fails and requires any change to the design, start that checklist over from the start after the change.
    • Really. It's important. The 2 extra minutes will save re-spinning a board.
  • Once checklists are all complete, wait 24 hours and take another brief look at the design before sending to manufacturing.
    • Don't have to re-run checklists, just look it over. It's surprising how many things jump out at you after not looking at a design for awhile.

Schematic Completion

  • Does the schematic pass ERC?
  • Is there a way to power the board?
  • Is there a way to program any MCU/CPLD/FPGAs on the board?
  • Are all clock signals routed to clock pins (if CPLD/FPGA)?
  • Are all MCUs on the board clocked (if required)?
  • Are required bypass capacitors included?
  • Are any required protection devices (e.g. PTC resettable fuses) included?
  • Are required test points included?
    • One small SMD point on every net that could conceivably require troubleshooting and does not appear on a connector
    • At least one PTH ground test point for scope/logic analyzer probes
    • PTH test points for nets that are very likely to require extensive troubleshooting, if space is available
    • 8/16-bit test/debug bus connector for CPLD/FPGA projects that could require logic analyzer connection
  • Is there a way for the user to receive status information (like LEDs)?
  • Are all nets named something useful (not N$)? Use the SHOW @ N$* command to check, if using EAGLE.
  • Are all nets properly classed (if required)?
  • Is there a way to set the address of the board (if on a multidrop bus)?
  • If an Arduino-compatible shield, make sure a reset button and power LED are included.
  • Are all connector pins rated for the current they will be carrying?
  • Do all specified PMICs have appropriate input voltage ranges, power levels, and topologies?
  • Are source/sink-only I/O connectors provided with the correct companion voltages?

PCB Completion

  • Is the DRC engine set up to match the board house being used?
  • Does the board pass DRC?
  • Are all connectors set up so that they won't interfere with each other?
    • Do a physical mockup if required to make sure everything fits in properly.
  • Are all connectors on the correct side of the board?
  • If the design has multiple boards with connectors between them, trace the path of a couple signals and make sure both connectors match up.
  • Has the footprint/pinout of any new components been double checked?
  • Are all sharp bends mitered?
  • Are all high-speed signals properly laid out?
  • Is the ground plane set up properly?
  • Are QFN/DFN/high-power parts properly thermally laid out?
  • Will the board plug into a standard 0.1" perfboard/breadboard (if applicable)?
  • Are mounting holes included if required?
  • Is the required silkscreen all added?
    • Connector/pin descriptions
    • Board name
    • Copyright/left information
    • URL (if possible to fit)
    • Revision number
    • ECO tracking boxes
    • Area for serial number
    • Strich
  • Switch to 3D view (if using Kicad) and check the following:
    • Does text on both sides of the board all face the same direction?
    • Do labels all appropriately describe what they're next to?
    • Will the test points be easy to get to once the board is stuffed?

CAM Completion

  • Do drills line up with pads?
  • Are vias tented appropriately?
  • Does mask extend between component pins?
  • Are test points left exposed on the correct side of the board?
  • Do silkscreen layers look reasonable and non-overlapping?
  • Does any silkscreen overlap drills?
  • Are required ground ties in place (if required)?
  • Are break-out tabs set up correctly?
  • Does board outline appear correct and contiguous?
  • Are slots/cutouts properly set up?
  • Are thermal pads left exposed and not covered in solder mask?
  • Are PTH pads excluded from paste layers?