Difference between revisions of "Project Peacock"

Revision as of 01:39, 11 September 2010

Project Peacock will be (in theory) a chipset for doing DVI/VGA display output from a microcontroller. It will consist of:

Display Controller MCU
- Communicate with host via I2C/SPI/RS232
- Will need a lot of I/O pins
  - RAM address bus - 22 pins
  - RAM data bus - 16 pins
  - RAM arbitration/handshaking - 6 pins
  - SPI/I2C/RS232 - 4 pins
  - Rough total - 48 I/O pins required
Display Driver CPLD
- Essentially just the digital part of a RAMDAC, constantly reads data from the RAM and spits it out to the output converter
- Since it's dealing with RAM anyway, it can handle the RAM details for the MCU (accept raw data from the MCU and write it to memory)
- Using a CPLD means the Display Controller MCU doesn't need to be super-fast
RAM
- SRAM
  - Far too expensive (~$200) for the amount needed
- PSRAM (Pseudo SRAM)/CellularRAM
  - SRAM interface but DRAM backend, simple to interface with and cheap (~$6)
  - Only available in VFBGA package meaning a four-layer board would be required, and hard to solder
- SDRAM
  - Inexpensive (~$5) and readily available
  - Easy non-BGA SMT packages
  - Harder to interface with, would need to have the CPLD handle RAM refreshing and other housekeeping
Output converter
- TMDS converter for DVI
- DAC for VGA

@@ Line 2: / Line 2: @@
 * Display Controller MCU
 ** Communicate with host via I2C/SPI/RS232
+** Will need a lot of I/O pins
+*** RAM address bus - 22 pins
+*** RAM data bus - 16 pins
+*** RAM arbitration/handshaking - 6 pins
+*** SPI/I2C/RS232 - 4 pins
+*** '''Rough total - 48 I/O pins required'''
 * Display Driver CPLD
 ** Essentially just the digital part of a RAMDAC, constantly reads data from the RAM and spits it out to the output converter
+** Since it's dealing with RAM anyway, it can handle the RAM details for the MCU (accept raw data from the MCU and write it to memory)
 ** Using a CPLD means the Display Controller MCU doesn't need to be super-fast
 * RAM