StrichLux/IO-DMX

The StrichLux IO-DMX module will provide one universe of DMX for the StrichLux system, and can be used as either an input module or an output module.

Project Status

• 2012-04-20: Programmed CPLD and it successfully blinks the status LED green/red! Also started working on the controller code.
• 2012-04-10 - 2012-04-20: Wrote Ruby code to read JEDEC files (ruby-jedec) and program MachXO2 CPLDs via the Bus Pirate
• 2012-04-04: Wishbone interface for DMX transmitter complete, as is mux for sharing the bus between SPI and DMX. Controller is the last Verilog piece pending.
• 2012-04-03: Verilog for DMX transmitter complete and tested in simulator.
• 2012-03-17: Schematic complete and checklist checked, starting and finished board layout/routing, CAM done, submitted to Laen for PCB manufacturing. Parts still need to be ordered.
• 2012-03-15: BOM is complete, schematic almost complete.
• 2012-03-14: Started schematizing/putting BOM together.

Specs

• One universe of DMX, no RDM support at least at the beginning.
• Can be used as an input or output module.
• Based around the Lattice MachXO2-256 CPLD

Architecture

<graph>graph {output: svg;}[ SPI Hardcore ] <-- Wishbone --> [ Module Supervisor Softcore ] <-- Wishbone --> [ DMX Softcore ]</graph>

Logic

• State INIT
  • Send READ command to Core Board w/ address 0
  • Enable DMX Transmission
  • State change to DMXWAIT
• State DMXWAIT
  • Wait for DMX "ready for channel data" interrupt
• State SPIREAD
  • Read 1 byte of data from Core Board
  • Send 1 byte of data to DMX output via Wishbone
  • Increment channel counter
  • State change to DMXWAIT if counter == 511
  • State change to IPDWAIT if not
• State IPDWAIT
  • Wait for inter-packet delay time
  • State change to INIT