Terasic DE1

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Revision as of 01:22, 13 June 2011 by SarahEmm (talk | contribs) (Posting a bunch of the pin definitions for the DE1.)
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The Terasic DE1 is an Altera FPGA development board.

Function FPGA Pin
Toggle 0 PIN_L22
Toggle 1 PIN_L21
Toggle 2 PIN_M22
Toggle 3 PIN_V12
Toggle 4 PIN_W12
Toggle 5 PIN_U12
Toggle 6 PIN_U11
Toggle 7 PIN_M2
Toggle 8 PIN_M1
Toggle 9 PIN_L2
Pushbutton 0 PIN_R22
Pushbutton 1 PIN_R21
Pushbutton 2 PIN_T22
Pushbutton 3 PIN_T21
LED Red 0 PIN_R20
LED Red 1 PIN_R19
LED Red 2 PIN_U19
LED Red 3 PIN_Y19
LED Red 4 PIN_T18
LED Red 5 PIN_V19
LED Red 6 PIN_Y18
LED Red 7 PIN_U18
LED Red 8 PIN_R18
LED Red 9 PIN_R17
LED Green 0 PIN_U22
LED Green 1 PIN_U21
LED Green 2 PIN_V22
LED Green 3 PIN_V21
LED Green 4 PIN_W22
LED Green 5 PIN_W21
LED Green 6 PIN_Y22
LED Green 7 PIN_Y21
Seven Segment Digit 0 Segment 0 PIN_J2
Seven Segment Digit 0 Segment 1 PIN_J1
Seven Segment Digit 0 Segment 2 PIN_H2
Seven Segment Digit 0 Segment 3 PIN_H1
Seven Segment Digit 0 Segment 4 PIN_F2
Seven Segment Digit 0 Segment 5 PIN_F1
Seven Segment Digit 0 Segment 6 PIN_E2
Seven Segment Digit 1 Segment 0 PIN_E1
Seven Segment Digit 1 Segment 1 PIN_H6
Seven Segment Digit 1 Segment 2 PIN_H5
Seven Segment Digit 1 Segment 3 PIN_H4
Seven Segment Digit 1 Segment 4 PIN_G3
Seven Segment Digit 1 Segment 5 PIN_D2
Seven Segment Digit 1 Segment 6 PIN_D1
Seven Segment Digit 2 Segment 0 PIN_G5
Seven Segment Digit 2 Segment 1 PIN_G6
Seven Segment Digit 2 Segment 2 PIN_C2
Seven Segment Digit 2 Segment 3 PIN_C1
Seven Segment Digit 2 Segment 4 PIN_E3
Seven Segment Digit 2 Segment 5 PIN_E4
Seven Segment Digit 2 Segment 6 PIN_D3
Seven Segment Digit 3 Segment 0 PIN_F4
Seven Segment Digit 3 Segment 1 PIN_D5
Seven Segment Digit 3 Segment 2 PIN_D6
Seven Segment Digit 3 Segment 3 PIN_J4
Seven Segment Digit 3 Segment 4 PIN_L8
Seven Segment Digit 3 Segment 5 PIN_F3
Seven Segment Digit 3 Segment 6 PIN_D4