PoE Shield

From Hackstrich

The PoE shield will be compatible software-wise with the official Arduino Ethernet Shield, but also supply power to the board via 802.3af-2003 compliant Power over Ethernet.

Project Status

  • Cancelling project as of 2012-12 as the official Arduino PoE shield is out, making this project not required.

Design, BOM, schematic, and PCB layout complete, PCBs and parts received, revision 1 board assembly is in progress. Power side assembly done, data side done except bypass caps and the Wiznet controller IC. Power supply side is outputting a well-regulated ~12v (stays in regulation and under temperature limits while under 100/250/500/750mA load), and data side is working well. Isn't reliably reseting on powerup, need to investigate that. Revision 2 PCBs and parts received, serial number 1 assembled, troubleshooting in progress. Board getting to SS-charge phase but not outputting anything on OUT, suspect issue on optocoupler/COMP pin. Building a second rev. 1 board so we can mess with it without breaking the only working one, but need R4, R10, BR1, BR2, Q1, U2 ordered again to finish it. MOSFET ratings are being exceeded (gate-source voltage), so need to correct that with a new MOSFET. Rev 3 board is hitting ~2V pulses on CS pin, which is terminating pulses early and not letting the supply come up fully. Found out 2011-06-28 that the wrong transformer was ordered/stuffed (13W2VERS instead of 13W3VERS). New one ordered and installed, output still not stable but better. Replacing D6 with the rev. 1 diode array causes the +7v output to be stable at 7v until load is placed on the supply, at which point it collapses again. D6 was under-rated for peak reverse voltage, need to replace it with something that can handle 30+ volts. SSA24-E3/61TGICT-ND should have all the specs we need. Will do more troubleshooting to figure out why the voltage collapses on load first. Seeing the optocoupler output go *down* as the input goes down, whereas these should be opposite of each other. More troubleshooting showed that sometimes the voltage doesn't collapse (usually when first starting troubleshooting) but sometimes later on it will start collapsing again. When under load, the output gains a ramp/step pattern which gets more severe with increasing load. Next step is to isolate just the feedback section, feed it from a function generator, and make sure the output is as expected.


Notes from Rev. 1 (SVN r51)

  • Package has silkscreen already, just none on bottom of rev. 1 boards: For LM5070 library part put a notation for where pin 1 goes.
  • Fixed in revision 2: C6 footprint does not match BoM (C6 should be 0603 or footprint to 1210)
  • Fixed in revision 2: D2/D3 have no silkscreen
  • Fixed in revision 2: Fix footprint on U2 (Pads are too far apart lengthwise)
  • Fixed in revision 2: Fix footprint for U3 (it's just generally wrong)
  • Fixed in revision 2: U3 pinout was wrong (all of the pins were in the wrong place)
  • Bigger test points (especially for prototypes), through hole especially.
  • Fixed in revision 2: R108 footprint is 0603 but BOM is 0402)
  • Fixed in revision 2 (new xfmr): Had wrong PoE transformer (1x3.3v 1x5v windings instead of 2x12v)
  • Fixed in revision 2 (changed to 0.5ohm): R9 should be 0.33Ω, not 33Ω. Need to recalculate this for revision 2 based on max allowed current draw
    • R9 at 1Ω (through hole) regulates alright at relatively low load.
  • Fixed in revision 2: Feedback resistors R16/R17 are backwards (i think), need to flip them/retest - Flipped, correctly limits to 11.8V with zero load.
  • Under 100mA load regulation is not correct. (This follows the R16/R17 swap.) Fixed by swapping R9 0.33Ω loop of wire for 1Ω through-hole resistor. See note about 1Ω resistor.
  • CS Resistor/Capacitor Filter needs to be right next to LM5070 to minimize induced noise. - fixed in rev2
  • INT jumper has no silkscreen. - Fixed in rev2; INT jumper is on the bottom with silkscreen on both sides. prototype PCB house does no do silkscreen on the bottom, hence top silkscreen.
  • Fixed in revision 2: D4 can be changed from a SMAJ90A to a SMAJ120A as Q1 can handle 200V.
  • Fixed in revision 2: /SCS should be connected to SS and SEN connected to /SS, not the other way around
  • Fixed in revision 2: Pins on the SPI connector to the Arduino are backwards (should be SCK, MISO, MOSI, SS from top down, not the other way around)

Ideas for Rev. 2

  • Implemented in rev. 2 - Could switch the main transformer to a POE13W3VERS-R (1.8/3.3/7V) or 7491192912 (3.3/5/12V) to avoid the need for secondary regulation all together
  • Implemented in rev. 2 - Should change DA1 to a MBRA210LT3G (and rename to D6 as it's no longer an array) as this can handle 2A (we need 0.75) rather than the 15A the current MBRB1530CT can handle, and is way smaller (SMA instead of D2PAK).

List of BoM Changes for Rev. 2

  • T1 changed to POE13W3VERS-R to add the 3.3v bus
  • X101 changed to tiny hybrid resonator instead of plain crystal, much smaller and still acceptable tolerances
  • C19 changed from 330uF 35V cap to 220uF 16V cap
  • C34-38, L4, R19, D5 , F3 added (for 3.3v output)
  • R16 changed from 0805 to 0402
  • R17 changed from 12.7k 0805 to 23.7k 0402 (for change from 12V to 7V output)
  • R9 changed from 33 to 0.5 (to fix current sense)
  • DA101 removed (connector LED now used for 100M not TX/RX)
  • DA1 changed to D6 (13A Schottky pack changed to single 2A diode)
  • D4 changed from SMAJ90A to SMAJ120A (no package change, both SMA)
  • CN1 changed from MagJack to plain jack
  • T2 added to replace previously-MagJack-contained magnetics
  • R20-R23, C39 added to replace previously-MagJack-contained TP termination components
  • SW1 added for reset button, changed to small SMD switch (original button missed on BOM)
  • Q1 changed to FDC3612CT-ND (smaller)

Known Issues with Rev. 2

  • Strich is on the bottom instead of the top
  • Fixed on rev 3 by switching to TSSOP - Silkscreen on LM5070 is missing
  • Fixed on rev 3 - Label for power LED is missing
  • Changed to proper crystal on BOM for rev 3 - Ordered Rev 1 crystal for X101
  • Changed to RJHSE-5380-ND without LEDs for rev 3 - Ordered CN1 has LED pins and LEDs
  • Fixed on rev 3 - U1 has no silkscreen or keepout outline on board
    • Fixed on rev 3 - TP5 (MOSFET CTL signal=MOSFET_GATE) is under U1
  • Duplicated on BOM for rev 3 - BOM has BR1, but schematic has BR2. They're the same part so it should be listed in BOM as BR1, BR2 and we should have ordered four total, not two.
  • Fixed on rev 3 - Would be nice to have a larger writing area for serial number.
  • Fixed on rev 3 (except for link/link speed)- Spread out LEDs just a tad and if possible move Link and link speed to the rest of the LEDs.
  • Board could be a little longer in order to give components a bit of spacing from the edge of the board and to make the shield closer to Arduino size. As it is the board is smaller than most shields.
  • Fixed on rev 3 - Caps near L1 should be moved farther away. (Silkscreen outline?)
  • Renamed on BOM for rev 3 - In BOM C19 (220µF 16V) should be called C24.
  • Fixed on rev 3 - FB3 needs to move away from C24 because it is difficult to solder.
  • Fixed quantity on BOM for rev 3 - C34 and C35 are on BOM but quantity doesn't match
  • Fixed on rev 3 - D5 has no silkscreen
  • Fixed quantity on BOM for rev 3 - R19 is in BOM but quantity is not right
  • Fixed on rev 3 - EAGLE has wrong component value for R17 - should be 23.7K
  • Fixed on rev 3 - Re-figure out termination as it's interfering with PoE
  • Larger test points
  • Fixed on rev 3 - TP6 is mislabelled as TP7
  • Fixed on rev 3 - Net called COMP_PULLDOWN should be called COMP_FILTER or COMP_RC
  • Changed MOSFET to IRFL4315TRPBF in rev 3 - MOSFET rating for Gate-Source Voltage is being exceeded, rated at 20V and is >25 in real use
  • Changed to TSSOP16 in rev 3 - Can't see under U1 to verify soldering, and it's very hard to solder.

LM Verification Problems

The MOSFET_GATE isn't receiving any pulses and we don't know why. We've verified the following pins as good:

1  - VIN (If it was bad we'd see nothing; the chip "works")
2  - RSIG (Passes signature phase of PoE Negotiation)
3  - RCLASS (Passes class phase of PoE Negotiation)
4  - UVLO (Would not proceed to charge load caps if broken)
5  - UVLORTN (See Pin 4-6, 8)
6  - RCLP (See Pin 4-6, 8)
7  - VEE (See Pin 1)
8  - RTN (See Pin 4-6)
9  - OUT ??????? (Assumed to be affected by another issue @ 02-21 18:22)
10 - VCC (Internal regulator output is OK; verified scope)
11 - FB ?????? (Can't say known good because we can't see solder joint @ 02-11 18:28)
12 - COMP ????? (Solder joint is fine, we see startup from LM @ 02-11 18:45)
13 - CS ????? (Can't say known good because we can't see solder joint, BUT we may GUESS that it is OK since we measure well  under <0.5 volt at R8 @ 02-11 18:33)
14 - RT (Measured ~2V output on pin under load, compared with rev 1)
15 - SS (See softstart cap charging)
16 - ARTN ????

Ideas for Rev 4

  • Done in rev 3. Change the package on the LM5070 to LM5070MTC-50-ND. This package is bigger but much cheaper and eliminates soldering questions.

Calculation Scratchpad

  • New reservoir capacitor for revision 2's 7V output
    • I(CF) = Vr
    • Old cap: 0.75/(0.00033*250000) = 0.009 (9mV)
    • New cap: 0.75/(0.00022*250000) = 0.014 (14mV)
      • This combined with the rating change from 35V to 16V reduces the footprint of C19 from 107mm2 to 43mm2
  • Reservoir capacitor for revision 2's 3.3V output
    • (0.20/(0.000033*250000)) = 0.024 (24mV)
  • MOSFET power calculations (rev. 1)
    • 2.54A peak
    • 4.24uS off, 2uS on
    • 1:2.12 on/off ratio = 32.05% duty cycle
    • ~400mW average power

Known Issues with Rev. 3

  • L1 needs a keepout border because C3 slightly under it/has clearance problems.
  • Give C15-C18 more spacing between them cos they stick together.
  • Change FB1-3 to FB101-103. They're for data.
    • Move currently-labeled FB3 away from C24
  • Give C19, C103, R103, R104 more spacing since they'll stick together.
  • Silkscreen on the bottom so we can see where parts go more easily.
  • Change SW1 should be SW101
  • LED1 needs silkscreen

Theory of Operation (Rev. 1)

Input Conditioning

Power is input via the first/second pair on the ethernet cable (Mode A) or third/fourth pair (Mode B). Each of these inputs gets fed to its own bridge rectifier (BR1 and BR2) which inverts the input voltage (if required) to a known polarity as the 802.3af spec allows for either polarity on the cable. The outputs from the rectifiers are bussed together, the positive running through F1 (a PTC 'fuse') to provide protection to the cable/PSE if something goes wrong in the power conversion circuitry.

The input power is then fed to C1 and C2 which bypass any high frequency noise present on the supply side of the choke to ground, then to L1 (a common mode choke) which blocks noise from the switcher from being fed back onto the ethernet cable by canceling out any common mode current (same on both + and - buses) but passing differential current (equal but opposite on the + and - buses), then to C3 and C4 which bypass any high frequency noise present on the switcher side of the choke to ground. L2 is then used for something, probably to filter out more noise?

D1 has no effect during normal operation, but if the input voltage exceeds 60V it will short the two power rails together ('crowbar'), which will make the PSE shut off power and/or trip F1. C5 bypasses any high-frequency noise present at this stage to ground.

Controller Programming

The UVLO (Undervoltage Lockout) feature of U1 shuts down the power supply when the voltage on the UVLO pin (referenced to the UVLORTN pin) is equal to or greater than 2.0V. R1 and R2 form a voltage divider to set the lockout to approximately 37V. R3 and C6 do something important I'm sure, but I have no idea what that is right now.

The frequency that the switcher operates at is set to 250kHz by connecting a 12.1kΩ resistor to the RT pin of U1 (1/(250000Hz*330*10^-12) = 12121Ω). The controller will vary the duty cycle to keep the output stable, but keep the frequency to the one set here.

To detect an 802.3af-compliant powered device (PD), the power sourcing equipment (PSE) applies a voltage from 2.8-10V and takes two measurements of impedance. If the impedance is between 23.75-26.25kΩ then the device is a PD and the PSE will move to the next phase (classification). U1 connects the RSIG pin to the VEE pin during this phase, which places R4 across the PSE. Once this phase ends, U1 disconnects RSIG in order to improve efficiency.

Once the signature is detected, the PSE applies 14.5-20.5V and measures the current drawn by the PD. The current is then looked up on a table to determine what class the device is, and it will be allowed to use the amount of power permitted by that class. The PoE shield currently 'advertises' itself as Class 1 (0.44-3.84W draw at the PD), but this may get changed later. For the classification phase, U1 connects the RCLASS pin to the VIN pin, which places R6 across the PSE. Once this phase ends, U1 disconnects RCLASS in order to improve efficiency.

When the classification phase has ended, the PSE will begin to supply full power. U1 will remain in a 'halt state' until the UVLO threshold has been reached, at which time it will connect VEE to RTN (via an internal power MOSFET) which will start charging the SMPS input capacitors C7, C8, and C9. The rate at which these capacitors will be allowed to charge (inrush current) is programmed to 150mA by a 107kΩ resistor connected to the RCLP pin, R5.


Primary Side

When the controller detects that the SMPS input capacitors C7, C8, and C9 are charged sufficiently, it starts switching Q1 (the main power MOSFET) at 250kHz (as programmed by the RT pin on U1). When the drive to Q1's gate (from U1's OUT pin) is pulled high Q1 conducts, storing energy from C7, C8, and C9 into the transformer by pulling one side of T1 to ground. When the gate drive is then pulled low, the the field in T1's primary collapses, transferring the energy to the other 3 windings. When this happens, a high voltage pulse is generated in T1's primary, which is snubbed by D3 and D4 when it exceeds 90V (to prevent damage to Q1).

Secondary Side

Controller Power