PoE Shield

The PoE shield will be compatible software-wise with the official Arduino Ethernet Shield, but also supply power to the board via 802.3af-2003 compliant Power over Ethernet.

Project Status

Design, BOM, schematic, and PCB layout complete, PCBs and parts received, revision 1 board assembly is in progress. Power side assembly done, data side done except bypass caps and the Wiznet controller IC. Power supply side is outputting a well-regulated ~12v (stays in regulation under 100/300mA load), data side assembly now in progress. Soldering the W5100 TQFP/SQFP80 is harder than expected.

Notes

Notes from Rev. 1 (SVN r51)

• Package has silkscreen already, just none on bottom of rev. 1 boards: For LM5070 library part put a notation for where pin 1 goes.
• Fixed in revision 2: C6 footprint does not match BoM (C6 should be 0603 or footprint to 1210)
• D2 has no silkscreen
• Fix footprint on U2 (Pads are too far apart lengthwise)
• Fix footprint for U3 (it's just generally wrong)
• U3 pinout was wrong (all of the pins were in the wrong place)
• Bigger test points (especially for prototypes), through hole especially.
• Fixed in revision 2: R108 footprint is 0603 but BOM is 0402)
• Had wrong PoE transformer (1x3.3v 1x5v windings instead of 2x12v)
• R9 should be 0.33Ω, not 33Ω. Need to recalculate this for revision 2 based on max allowed current draw
  • R9 at 1Ω (through hole) regulates alright at relatively low load.
• Fixed in revision 2: Feedback resistors R16/R17 are backwards (i think), need to flip them/retest - Flipped, correctly limits to 11.8V with zero load.
• Under 100mA load regulation is not correct. (This follows the R16/R17 swap.) Fixed by swapping R9 0.33Ω loop of wire for 1Ω through-hole resistor. See note about 1Ω resistor.
• CS Resistor/Capacitor Filter needs to be right next to LM5070 to minimize induced noise.
• INT jumper has no silkscreen.

Ideas for Rev. 2

• Could switch the main transformer to a POE13W3VERS-R (1.8/3.3/7V) or 7491192912 (3.3/5/12V) to avoid the need for secondary regulation all together

Theory of Operation (Rev. 1)

Input Conditioning

Power is input via the first/second pair on the ethernet cable (Mode A) or third/fourth pair (Mode B). Each of these inputs gets fed to its own bridge rectifier (BR1 and BR2) which inverts the input voltage (if required) to a known polarity as the 802.3af spec allows for either polarity on the cable. The outputs from the rectifiers are bussed together, the positive running through F1 (a PTC 'fuse') to provide protection to the cable/PSE if something goes wrong in the power conversion circuitry.

The input power is then fed to C1 and C2 which bypass any high frequency noise present on the supply side of the choke to ground, then to L1 (a common mode choke) which blocks noise from the switcher from being fed back onto the ethernet cable by canceling out any common mode current (same on both + and - buses) but passing differential current (equal but opposite on the + and - buses), then to C3 and C4 which bypass any high frequency noise present on the switcher side of the choke to ground.

D1 has no effect during normal operation, but if the input voltage exceeds 60V it will short the two power rails together ('crowbar'), which will make the PSE shut off power and/or trip F1. C5 bypasses any high-frequency noise present at this stage to ground.

Controller Programming

The UVLO (Undervoltage Lockout) feature of U1 shuts down the power supply when the voltage on the UVLO pin (referenced to the UVLORTN pin) is equal to or greater than 2.0V. R1 and R2 form a voltage divider to set the lockout to approximately 37V. R3 and C6 do something important I'm sure, but I have no idea what that is right now.

To detect an 802.3af-compliant powered device (PD), the power sourcing equipment (PSE) applies a voltage from 2.8-10V and takes two measurements of impedance. If the impedance is between 23.75-26.25kΩ then the device is a PD and the PSE will move to the next phase (classification). U1 connects the RSIG pin to the VEE pin during this phase, which places R4 across the PSE. Once this phase ends, U1 disconnects RSIG in order to improve efficiency.

Once the signature is detected, the PSE applies 14.5-20.5V and measures the current drawn by the PD. The current is then looked up on a table to determine what class the device is, and it will be allowed to use the amount of power permitted by that class. The PoE shield currently 'advertises' itself as Class 1 (0.44-3.84W draw at the PD), but this may get changed later. For the classification phase, U1 connects the RCLASS pin to the VIN pin, which places R6 across the PSE. Once this phase ends, U1 disconnects RCLASS in order to improve efficiency.

When the classification phase has ended, the PSE will begin to supply full power. U1 will remain in a 'halt state' until the UVLO threshold has been reached, at which time it will connect VEE to RTN (via an internal power MOSFET) which will start charging the SMPS input capacitors C7, C8, and C9. The rate at which these capacitors will be allowed to charge (inrush current) is programmed to 150mA by a 107kΩ resistor connected to the RCLP pin, R5.